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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago

Hie,

Sorry, my mistake. I accidently typed AVMM_SRIOV instead of AVST-SRIOV. You are correct, we don't offer AVMM_SRIOV interface.

I needed to know which PCIe interface are you using currently, If you are using AVST-SRIO, then observed simulation is expected as the Intel-BFM don't support Gen3 Phase 2 and Phase 3 equalization.

Please advice accordingly.

Regards,

Nathan