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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago

​Hie,

I will to duplicate the issue in-house to debug further. Could you provide your simulation files (zipped). In the meanwhile, can you the following:

  1. disable fast_sim
  2. ensure following are disabled in your Arria 10 Hard IP for PCIe under Phy Characteristics tab:
  • Enable Rx polarity inversion soft logic
  • enable soft DFE controller IP

If not, please disable it and retry simulation.

Also change the Requested equalization Far end Tx Preset to Preset 0 if you are recompiling.

Regards,

Nathan