Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hie RamaMohan,

fast_sim does help to speed up the simulation related to analog functions to be shorter such as PLL locking,CDR locking and analogue calibration. Hence, its good you have enabled it.

However, you seem to be observing HiZ. This is typically caused by some of the IP's input ports floating upon starting simulation. I can't be certain this is the root cause, but firstly, please check if all you clocks are driven and resets have an initial value upon staring simulation.

Secondly, please check the FPGA is connected to the other end (if FPGA is endpoint, it is connected to a Root Port). This way the TX lines will observe a Rx and won't be showing HiZ for a long time.

Also do advice, which Arria 10 PCIe interface, configuration is being used (ex: AVMM Gen3x8 128bit) and which simulator is showing this behavior.

Regards,

Nathan

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