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RamaMohan's avatar
RamaMohan
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7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

​Is there an option to configure AVMM with SRIOV enabled? My interactions with Intel confirmed that this configuration wasn't available. So, is it fine if I attach just the .ip file?

Thanks,

RamaMohan