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RamaMohan's avatar
RamaMohan
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7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi Nathan,

Thanks for the reply. The HiZ being observed is at a point LTSSM on both (RC and EP) sides had proceeded to recovery speed state, which implies all the connectivity on serial interface side and input side is fine. We have physically verified the same in waveform as well.

Please refer to the attached snapshot of waveform showing A10 PCIe HIP signals which indicate this condition. The LTSSM state is also captured in the waveform.

We are using Arria10 PCIe Gen3, x8, 256bit is the configuration being used.

Thanks,

RamaMohan