Forum Discussion
Honored ContributorInterfacing custom logic to SDRAM controller IP without using NIOS
Hello,
Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to test that I can use the SDRAM controller in my SOPC Builder system: writing 1 x 16-bit word of data to SDRAM using my own Avalon MM Master (in Verilog). The code is: // Shift register for host_rst_l always @(posedge host_clk or negedge host_rst_l) begin if (~host_rst_l) host_rst_l_sr <= 2'b0; else host_rst_l_sr <= {host_rst_l, host_rst_l_sr[1]}; end // State Machine which writes to and reads from SDRAM Controller always @(posedge host_clk or negedge host_rst_l) begin if (~host_rst_l) begin state <= 4'h0; sdram_read <= 1'b0; sdram_write <= 1'b0; sdram_writedata <= 16'h0; debug_sdram_readdata <= 8'h0; sdram_byteenable <= 2'b0; end else if (host_rst_l_sr == 2'b10) state <= 4'h1; // Write Operation else if (state == 4'h1) begin state <= state + 1'b1; sdram_write <= 1'b1; sdram_writedata <= 16'h28; sdram_addr <= 24'h0; sdram_byteenable <= 2'b11; end else if ((state == 4'h2)&(~sdram_waitrequest)) begin state <= state + 1'b1; sdram_write <= 1'b0; end // Read Operation else if (state == 4'h3) begin state <= state + 1'b1; sdram_read <= 1'b1; sdram_addr = 24'h0; sdram_byteenable = 2'b11; end else if ((state == 4'h4)&(sdram_readdatavalid)&(~sdram_waitrequest)) begin state <= 4'h0; debug_sdram_readdata <= sdram_readdata[7:0]; sdram_read <= 1'b0; end end I don't get any response from the SDRAM controller. Can anyone see what I'm doing wrong - my understanding is that the above code complies with the Avalon MM spec. best regards, John14 Replies
Altera_ForumHave you look at Altera Avalon-MM templates code yet?
http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=1&wt.oss_r=1&wt.oss=avalon-mm- Altera_Forum
Yes - but thought it looked straightforward to write my own interface so didn't use the template.
Have you used the template? Would you recommend it? John - Altera_Forum
1. You generated SDRAM controller from Megacore IP and plugged into SOPC builder.
2. Now, you write your own custom Avalon-MM to write/read from SDRAM For me, I have SDRAM controller from IP. I connected the SDRAM to SGDMA mm_to_st and st_to_mm in SOPC. Now, I write my own custom Avalon-ST protocol in between mm_to_st and st_to_mm to verify that my interface is working correct. If you want to go this way, SGDMA. I will post you the custom interface to verify it. Sean - Altera_Forum
Thanks Sean,
We don't need to use scatter gather, we have some very simple dma functionality incorporated into our own IP. I'm going to see if I can learn anything from the BFM in the Avalon Verification Suite and if that fails, I will try to use the Avalon MM template. If everything fails, I may come back to you for the SG interface. Thanks again for the response - much appreciated, John - Altera_Forum
Hello Johnnie,
I'd like to know if you made any advance with this. I'm working on a project in which I need an interface with the SDRAM without a NIOS II. The SOPC Builder is a great tool but it doesn´t let us (by default) use such components with our own HW in Verilog as it provides the Avalon MASTER (NIOS II). I will be reading about this Avalon templates but I want to know about your experience with it, so I can have a little bit more of background. As you can see I'm an "absolute beginner" in this forum, so I haven't worked with external RAM yet. BTW, I'm using the Terasic Board DE0-Nano. - Altera_Forum
If you are looking for a clean template I recommend that pattern reader and writter cores in the Qsys tutorial design. They are basically the same masters as the modular SGDMA only I ripped a bunch of stuff out of them that wasn't necessary for swamping memory. They perform MM on one side and ST on the other so if you want MM to MM just bolt the ST interfaces together. To control the masters there is a command streaming port where you tell the masters stuff like source address, destination address, transfer length, etc.....
These masters will most likely become the new Avalon templates after I create some gasket cores to allow you to access them from outside SOPCB/Qsys. - Altera_Forum
So, to summarize things up... which is the best way to interface an SDRAM without Nios II?
- SOPC SDRAM controller and custom Avalon MM Master? - Megawizard SDRAM controller? - Qsys? - Custom Logic, propietary FSM? And.. may I focus this a little bit more to my application? I'm making a large scale Datalogger (256 16bit signals) and I need to save many samples from the same sensor in RAM in order to be able to make some processing before storing them in a NAND Flash. - Altera_Forum
Which Megawizard SDRAM controller are you referring to? I'm not familiar with the "Altera SDRAM Controller" besides the one that comes in SOPC Builder/Qsys. The only SDR SDRAM controllers I see in the megawizard are the ones from CAST and Northwest Logic. I think the Microtronix multiport front end controller supports SDR too.
I typically recommend that people just build their own Avalon masters and connect to the memory using SOPC Builder or Qsys. These days I use Qsys to do this because: 1) Hierarchy 2) High performance fabric 3) I can add more masters by clicking buttons, doing this in custom logic requires lots of HDL changes which I consider a waste of time - Altera_Forum
Thank you BadOmen, now.. as i said.. I'm a beginner but I wanted to start with the right foot. I'm not sure how to create this Avalon MM Master, so I will begin by reading all about it and how to use the templates, but I would appreciate any other recommendations even though I have a better perception of the problem.
- Altera_Forum
Some recommendations that should make it easier to implement and hit a higher Fmax:
- If possible make sure all accesses are aligned and are full words - Avoid bursting unless you absolutely need bursting, the SOPC/Qsys SDRAM controller doesn't support bursting so if you use it no point making a bursting master - Iscolate the data using FIFOs, so if you have data to write to memory shove it into a FIFO first and base the writing on the FIFO not being empty. For reads this is a little more complicated* * Other stuff for reads: - Decouple the address and data for read transfers by including a FIFO in the master for read data to return - Keep track of the number of outstanding reads and make sure the number of reads outstanding never exceeds the amount of space left in the FIFO If you look at the masters in the Qsys tutorial and ignore the burst stuff you'll see all this stuff being implemented.
