Interfacing custom logic to SDRAM controller IP without using NIOS

Some recommendations that should make it easier to implement and hit a higher Fmax:

- If possible make sure all accesses are aligned and are full words

- Avoid bursting unless you absolutely need bursting, the SOPC/Qsys SDRAM controller doesn't support bursting so if you use it no point making a bursting master

- Iscolate the data using FIFOs, so if you have data to write to memory shove it into a FIFO first and base the writing on the FIFO not being empty. For reads this is a little more complicated*

* Other stuff for reads:

- Decouple the address and data for read transfers by including a FIFO in the master for read data to return

- Keep track of the number of outstanding reads and make sure the number of reads outstanding never exceeds the amount of space left in the FIFO

If you look at the masters in the Qsys tutorial and ignore the burst stuff you'll see all this stuff being implemented.