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Altera_Forum
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15 years ago

Interfacing custom logic to SDRAM controller IP without using NIOS

Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello Johnnie,

I'd like to know if you made any advance with this.

I'm working on a project in which I need an interface with the SDRAM without a NIOS II. The SOPC Builder is a great tool but it doesn´t let us (by default) use such components with our own HW in Verilog as it provides the Avalon MASTER (NIOS II).

I will be reading about this Avalon templates but I want to know about your experience with it, so I can have a little bit more of background.

As you can see I'm an "absolute beginner" in this forum, so I haven't worked with external RAM yet.

BTW, I'm using the Terasic Board DE0-Nano.