Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Interfacing custom logic to SDRAM controller IP without using NIOS

Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

So, to summarize things up... which is the best way to interface an SDRAM without Nios II?

- SOPC SDRAM controller and custom Avalon MM Master?

- Megawizard SDRAM controller?

- Qsys?

- Custom Logic, propietary FSM?

And.. may I focus this a little bit more to my application?

I'm making a large scale Datalogger (256 16bit signals) and I need to save many samples from the same sensor in RAM in order to be able to make some processing before storing them in a NAND Flash.