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Altera_Forum
Honored Contributor
Honored ContributorInterfacing custom logic to SDRAM controller IP without using NIOS
Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_ForumHonored Contributor
Honored ContributorIf you are looking for a clean template I recommend that pattern reader and writter cores in the Qsys tutorial design. They are basically the same masters as the modular SGDMA only I ripped a bunch of stuff out of them that wasn't necessary for swamping memory. They perform MM on one side and ST on the other so if you want MM to MM just bolt the ST interfaces together. To control the masters there is a command streaming port where you tell the masters stuff like source address, destination address, transfer length, etc.....
These masters will most likely become the new Avalon templates after I create some gasket cores to allow you to access them from outside SOPCB/Qsys.
