Interfacing custom logic to SDRAM controller IP without using NIOS

If you are looking for a clean template I recommend that pattern reader and writter cores in the Qsys tutorial design. They are basically the same masters as the modular SGDMA only I ripped a bunch of stuff out of them that wasn't necessary for swamping memory. They perform MM on one side and ST on the other so if you want MM to MM just bolt the ST interfaces together. To control the masters there is a command streaming port where you tell the masters stuff like source address, destination address, transfer length, etc.....