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Altera_Forum
Honored Contributor
Honored ContributorInterfacing custom logic to SDRAM controller IP without using NIOS
Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_ForumHonored Contributor
Honored ContributorWhich Megawizard SDRAM controller are you referring to? I'm not familiar with the "Altera SDRAM Controller" besides the one that comes in SOPC Builder/Qsys. The only SDR SDRAM controllers I see in the megawizard are the ones from CAST and Northwest Logic. I think the Microtronix multiport front end controller supports SDR too.
I typically recommend that people just build their own Avalon masters and connect to the memory using SOPC Builder or Qsys. These days I use Qsys to do this because: 1) Hierarchy 2) High performance fabric 3) I can add more masters by clicking buttons, doing this in custom logic requires lots of HDL changes which I consider a waste of time
