DZuck1
Occasional Contributor
7 years agoIntel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL
Hi,
I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly.
The testbench executes all the way to the end with CRCs reported back to be all 0's for R, G & B. The vbid[3] - NoVideoStream_Flag is high during the entire simulation.
All of the signals mentioned in Figure 36 of UG-01131 (RX Video Waveform) are static for the entire simulation. I would expect the received video to look similar to the timing diagram of that figure.
Is there something wrong with the simulation or am I not setting it up correctly?