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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Intel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL

Hi, I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly. The testbench...
watari's avatar
watari
Icon for New Contributor rankNew Contributor
7 years ago

Hi DZukc1

Signal "rx_vid_clk" is input signal and this frequency is ex. 162MHz.

So, would you input rx_vid_clk as 162MHz ?

This module (dp_sink) is generated some signals (ex. rx_vid_sol, rx_vid_eol, rx_vid_sof, r_vid_eof and so on) by rx_vid_clk.

BTW, if rx_vid_clk already toggled, would you wait for one frame ?

These signals are generated by MSA, VBID and so on.

Best regards

DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
I expect to some transitions on rx_vid_sol, rx_vid_eol, rx_vid_sof, r_vid_eof, rx_vid_valid and rx_vid_data.