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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Intel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL

Hi, I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly. The testbench...
watari's avatar
watari
Icon for New Contributor rankNew Contributor
7 years ago

I see.

Would you make sure CDC setting at parameter in this IP ?

This module has many CDC logic.

If clock frequency setting is wrong, DP Sink malfunction.

Best regards,

  • DZuck1's avatar
    DZuck1
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    I used the User Guide's process to generate the example design and that is what I am trying to simulate.