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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Intel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL

Hi, I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly. The testbench...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Sir, do you have chance to try the simulation with latest version 18.1 or other simulator like modelsim?

By the way, Arria 10 DP do not have CDC or CRC setting.

DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
The only simulator I have access to is Aldec Active-HDL. The displayport core has a debug CRC setting that can be enabled to confirm the data received into the core. The sample design enables it by default. The User Guide shows that the CRC shouldn’t be 0.