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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Intel DisplayPort Arria 10 Sample Project Not Simulating Correctly in Aldec Active-HDL

Hi, I am trying to simulate the Intel DisplayPort Arria 10 Sample Project(Quartus Prime v17.0) in Aldec Active-HDL (v10.3 64 bit) and don't think the simulation is working correctly. The testbench...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Thanks!

I run the simulation in modelsim_se edition and I also see the same observation (all zero). Let me check further on this.

But frankly speaking, for DP, usually we directly validate the IP on actual hardware and seldom run the simulation.

DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
I am trying to re-run it with Quartus 18.1 and Aldec 10.5a but am not hopeful that it will work. I am a little curious why the text output of the testbench in the user guide is different than mine. The user guide has a measured frequency of 270 MHz which my simulation does not have. My simulation has 135 MHz twice and the user guide has it only once.