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Arune34's avatar
Arune34
Icon for New Contributor rankNew Contributor
12 months ago

Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data

Hi everyone,

I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core.

My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double width transfer" option. I referred the 'E-Tile Transceiver PHY User Guide (UG-20056)' about the connectivity of parallel data using double width transfer. It seems that the TX/RX parallel data ports of the Transceiver are 80-bit wide, but the Table 32. in the user guide shows connectivity of 160-bit wide data. I've attached the snapshot for your reference.

 

Please help to clarify my doubt and to integrate my design with the Transceiver.

Thanks in advance,
Arun

Jesd

5 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    Hi,

    I believe that my comments helped you to resolve your query. Hence, I am setting this case to closure. However, it will still be open for the community members to comment upon.


    Regards


  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    The document has correct information. When double data width is enabled, the bus width will be 64 x 2 = 128. The bit mapping is also provided in the table and also other tables below that.


    Regards


  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    11 months ago

    Hi,

    The table that you mentioned, shows the data bit placement when the TX/RX PMA Interface Width = 64 and Enable TX/RX double width transfer = Enabled. The max parallel data width can be 64 bits.

    For your requirement, you may need multiple E-tiles, but sadly there is no part with 2 E-tiles in Agilex 7. You will have to change the part that has been selected to accommodate more data width, like F-tile. 3.5.1. Parallel Data Mapping Information


    Regards


    • Arune34's avatar
      Arune34
      Icon for New Contributor rankNew Contributor
      11 months ago

      Hi Ash_R,

      Thanks for your response. I understand that the table shows the data bits placement, but my concern is that, the table shows the bits upto 128 (interface width = 64 & enabled double width transfer), on the other side the Intel Quartus tool generates only 64 bits using the IP parameter editor. Now I get to know from your point that, E-Tile doesn't support more than 64-bit interface width, but this should be mentioned in the 'E-Tile Transceiver PHY User Guide (UG-20056)' document.

      Thanks and Regards,

      Arun

  • WeiHanT_Intel's avatar
    WeiHanT_Intel
    Icon for Moderator rankModerator
    11 months ago

    Thank you for reaching out to Altera Community Forum. Our SME is currently out of the office and will be returning on 3-Jan-2025. We apologize for any inconvenience this may cause. In the interim, we welcome the community to contribute with any questions, and we’ll strive to offer support whenever possible.