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Arune34's avatar
Arune34
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12 months ago

Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data

Hi everyone, I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core. My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double ...
Jesd
Ash_R_Intel's avatar
Ash_R_Intel
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11 months ago

Hi,

The table that you mentioned, shows the data bit placement when the TX/RX PMA Interface Width = 64 and Enable TX/RX double width transfer = Enabled. The max parallel data width can be 64 bits.

For your requirement, you may need multiple E-tiles, but sadly there is no part with 2 E-tiles in Agilex 7. You will have to change the part that has been selected to accommodate more data width, like F-tile. 3.5.1. Parallel Data Mapping Information


Regards


Arune34's avatar
Arune34
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11 months ago

Hi Ash_R,

Thanks for your response. I understand that the table shows the data bits placement, but my concern is that, the table shows the bits upto 128 (interface width = 64 & enabled double width transfer), on the other side the Intel Quartus tool generates only 64 bits using the IP parameter editor. Now I get to know from your point that, E-Tile doesn't support more than 64-bit interface width, but this should be mentioned in the 'E-Tile Transceiver PHY User Guide (UG-20056)' document.

Thanks and Regards,

Arun