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Arune34's avatar
Arune34
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1 year ago

Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data

Hi everyone, I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core. My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double ...
Jesd
Weihan_T_Altera's avatar
Weihan_T_Altera
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1 year ago

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