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Arune34
New Contributor
New ContributorIntel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data
Hi everyone, I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core. My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double ...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
I believe that my comments helped you to resolve your query. Hence, I am setting this case to closure. However, it will still be open for the community members to comment upon.
Regards
