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New Contributor

1 year ago

Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data

Hi everyone, I have doubt in the parallel data interface of Intel Agilex 7 FPGA's E-Tile Transceiver PHY IP core. My design has a parallel data of 128-bit width, So I used the "Enable TX/RX double ...

Jesd

Ash_R_Intel

Regular Contributor

1 year ago

Hi,

The table that you mentioned, shows the data bit placement when the TX/RX PMA Interface Width = 64 and Enable TX/RX double width transfer = Enabled. The max parallel data width can be 64 bits.

For your requirement, you may need multiple E-tiles, but sadly there is no part with 2 E-tiles in Agilex 7. You will have to change the part that has been selected to accommodate more data width, like F-tile. 3.5.1. Parallel Data Mapping Information

Regards

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Intel Agilex 7 FPGA E-Tile Transceiver PHY - Parallel Data

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