H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

Question

wincent_altera · Answer

Hi,I am the same Application Engineer who providing answer at the below forum (that you sent in this reply)https://community.intel.com/t5/FPGA-Intellectual-Property/MCDMA-PCIe-what-is-frequency-of-coreclkout-hip/m-p/1446396/highlight/true#M26874Yes, your understanding is correct for "coreclkout_hip is a 250MHz clock as stated in the User-Guide, and the clock shown by the timing analyzer is a clock internal of the PCIe HIP Core."There is some confusing between the timing report comparing to the userguide, I will report to internal team again, hope they will fix this either in Quartus/user guide to avoid causing any confuse.Regards,Wincent_Intelp/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

wincent_altera · Answer

Hi ,For the coreclkout_hip you may refer to under 6.1.3. Clocks and Resethttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avmm.pdf If you are using avmm HIP, coreclkout_hip can be used for the application logic.coreclkout_hip clock should be used as the clock for PCIe "user" logic.Hope this clarified.Regards,Wincent_Intel

tm1701 · Answer

According to the timing analyzer the logic I clock with coreclkout_hip has the following clock as clock input:

pcie_ctrl|root_port_cc|rp|rp_ip_x8_gen3|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0

However the clock is a 500MHz clock according to the Timing Analyzer, whereas the User Guide states that coreclkout_hip is a 250MHz clock, if the IP-Core is configured as Gen3 x8.

The following picture shows the timing analyzers clocks summary output (the clock in questions is at row number 36):

There is another post in the forums where it is discussed why the clock is shown as a 500MHz clock:

https://community.intel.com/t5/FPGA-Intellectual-Property/MCDMA-PCIe-what-is-frequency-of-coreclkout-hip/m-p/1446396/highlight/true#M26874

If I understand it correctly the conclusion of the discussion was, that coreclkout_hip is a 250MHz clock as stated in the User-Guide, and the clock shown by the timing analyzer is a clock internal of the PCIe HIP Core.

Is this correct?

My confusion as of how I constrain my logic driven by coreclkout_hip remains. Can I safely refer to

pcie_ctrl|root_port_cc|rp|rp_ip_x8_gen3|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0

in my timing constraints as if it were coreclkout_hip, despite the frequency difference?

If not how to I create a proper clock target for coreclkout_hip?

Please let me know if I can provide you with any further information.

Thank you!

wincent_altera · Answer

HiThanks for confirming the answer, glad that I am able to help you.Hence, I will close my loop on this case and this thread will be transitioned to community support.If you have a new question, feel free to open a new thread to get support from Intel experts.Otherwise, the community users will continue to help you on this thread. Thank youIf your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. Regards,Wincent_Intelp/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

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