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tm1701's avatar
tm1701
Icon for New Contributor rankNew Contributor
2 years ago

H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

Hello, we want to properly constrain our application logic of a design using the H-Tile Avalon Streaming PCIe Hard IP-Core. The Application Logic is driven by coreclkout_hip then later we have some...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi

Thanks for confirming the answer, glad that I am able to help you.

Hence, I will close my loop on this case and this thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.