H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

According to the timing analyzer the logic I clock with coreclkout_hip has the following clock as clock input:

pcie_ctrl|root_port_cc|rp|rp_ip_x8_gen3|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0

However the clock is a 500MHz clock according to the Timing Analyzer, whereas the User Guide states that coreclkout_hip is a 250MHz clock, if the IP-Core is configured as Gen3 x8.

The following picture shows the timing analyzers clocks summary output (the clock in questions is at row number 36):

There is another post in the forums where it is discussed why the clock is shown as a 500MHz clock:

https://community.intel.com/t5/FPGA-Intellectual-Property/MCDMA-PCIe-what-is-frequency-of-coreclkout-hip/m-p/1446396/highlight/true#M26874

If I understand it correctly the conclusion of the discussion was, that coreclkout_hip is a 250MHz clock as stated in the User-Guide, and the clock shown by the timing analyzer is a clock internal of the PCIe HIP Core.

Is this correct?

My confusion as of how I constrain my logic driven by coreclkout_hip remains. Can I safely refer to

pcie_ctrl|root_port_cc|rp|rp_ip_x8_gen3|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0

in my timing constraints as if it were coreclkout_hip, despite the frequency difference?

If not how to I create a proper clock target for coreclkout_hip?

Please let me know if I can provide you with any further information.

Thank you!