H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

Hi,

I am the same Application Engineer who providing answer at the below forum (that you sent in this reply)

https://community.intel.com/t5/FPGA-Intellectual-Property/MCDMA-PCIe-what-is-frequency-of-coreclkout-hip/m-p/1446396/highlight/true#M26874

Yes, your understanding is correct for "coreclkout_hip is a 250MHz clock as stated in the User-Guide, and the clock shown by the timing analyzer is a clock internal of the PCIe HIP Core."

There is some confusing between the timing report comparing to the userguide, I will report to internal team again, hope they will fix this either in Quartus/user guide to avoid causing any confuse.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.