Forum Discussion
tm1701
New Contributor
New ContributorH-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip
Hello, we want to properly constrain our application logic of a design using the H-Tile Avalon Streaming PCIe Hard IP-Core. The Application Logic is driven by coreclkout_hip then later we have some...
Wincent_Altera
Regular Contributor
Regular ContributorHi ,
For the coreclkout_hip you may refer to under 6.1.3. Clocks and Reset
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avmm.pdf
If you are using avmm HIP, coreclkout_hip can be used for the application logic.
coreclkout_hip clock should be used as the clock for PCIe "user" logic.
Hope this clarified.
Regards,
Wincent_Intel
