Forum Discussion

Yuriah's avatar
Yuriah
Icon for New Contributor rankNew Contributor
1 month ago

Fitter cannot ...

I am trying to set up a basic SDI transmitter on an Agilex 5. Currently, my setup is a 148.5 MHz refclk, a GTS PMA Direct PHY IP configured for 12G SDI, a GTS Reset Sequencer, and a GTS System PLL configured to take in the refclk and output 742.5 MHz (this is based on the minimum system PLL frequency recommendation in the SDI II IP documentation). I have my serial output differential pair on pins BE129 and BE126 which are the GTS Left 1B TX 0 channels, and my refclk coming in as a differential pair on pins AY120 and AY115 which are the refclk pins for GTS Left 1B. According to the documentation for the SoM, these refclk pins should be configured to 148.5 MHz.

For some reason, when I try to compile, the fitter fails in the plan stage with error 14566 "The Fitter cannot place 1 periphery component due to conflicts with existing constraints (1 I/O pad). Fix the errors described in the submessages, and then rerun the Fitter." The submessages read, "Illegal constraint of I/O pad to the location PIN_AY115" (175019), "No legal location could be found out of 1 considered location. Reasons why each location could not be used are summarized below:" (16234), "There is no routing connectivity between the I/O pad and the destination I/O input buffer" (175006), "The I/O pad could not be placed in any location to satisfy its connectivity requirements" (175022), and "The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements" (175022).

There isn't very much logic surrounding the system (basically just a counter to create some dummy input data), so I'm not sure why it wouldn't be able to connect specifically the n side of the refclk.

Has anyone encountered similar issues/errors and could maybe point me in the right direction? Any help would be appreciated.

4 Replies

  • Yuriah's avatar
    Yuriah
    Icon for New Contributor rankNew Contributor

    I figured out the problem. I was trying to have an always block assign the GTS PLL refclk_rdy signal based on the positive edge of the 148.5 MHz refclk. Turns out the GTS refclk pins cannot be accessed in the main fabric.

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor

      Hi Yuriah,

      Just to confirm, means the problem is solved ?
      IF yes, I am glad that you able to resolved it, thanks for sharing with me how you make it right.

      Let me know if there is anything else I can help you.

      Regards,
      Wincent

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi,

     

    1. May I know which device of Agilex 5 that you are using ? 
      Premium devkit , Modular devkit or this is custom board ?
    2. Do you try to compile the design example itself without modifying anything ? Just try to narrow the problem

    At the meantime, can you please try try to assign another similar standard pin to it and check it the error happen the same ?

    From the error seen like you not choosing the correct I/O bank and supports required voltage standard feature for the IP
    I would suggest to refer to the design example as a good start.

     

    Regards,
    Wincent_Altera

  • Yuriah's avatar
    Yuriah
    Icon for New Contributor rankNew Contributor

    I forgot to mention that I am using Quartus 25.3, but I had the same problem in 25.1.1.