dummy core between two VIP using SOPC builder

Hi all

I am working on a simple Verilog block that should interface with avalon-ST and avalon-ST protocol.

right now, the code I've written for sopc builder is this

--- Quote Start ---

module dummy_block(

din_endofpacket,

din_startofpacket,

clock,

dout_ready,

din_valid,

din_data,

dout_endofpacket,

dout_startofpacket,

din_ready,

dout_valid,

dout_data

);

//the sink

input clock;

input din_endofpacket;

input din_startofpacket;

output dout_ready;

input din_valid;

input [15:0] din_data;

//the source

output dout_endofpacket;

output dout_startofpacket;

input din_ready;

output dout_valid;

output [15:0] dout_data;

wire reset;

reg [7:0] data_y;

reg [7:0] data_c;

reg din_endofpacket_i,din_startofpacket_i,din_valid_i,din_ready_i,dout_valid_i;

assign dout_ready = din_ready_i;

assign dout_endofpacket = din_endofpacket_i;

assign dout_startofpacket = din_startofpacket_i;

assign dout_valid = din_valid_i;

assign dout_data[15:0]={data_y,data_c};

assign reset=1'b0;

always@(posedge clock or posedge reset)

begin

if (reset) begin

data_y<=8'b0;

data_c<=8'b0;

din_endofpacket_i<=1'b0;

din_startofpacket_i<=1'b0;

din_valid_i<=1'b0;

din_ready_i<=1'b0;

end

else begin

data_y<=din_data[15:8];

data_c<=din_data[7:0];

din_endofpacket_i<=din_endofpacket;

din_startofpacket_i<=din_startofpacket;

din_valid_i<=din_valid;

din_ready_i<=din_ready;

end

end

endmodule

--- Quote End ---

I WANT to use registers, becouse next I'll have to work on video pakets.

If i use only simple assignments it works fine.

If I use registers, the system does not work at all.

Input and output signal are correctly interfaced with related signals on avalon-ST (i don't know how to post the sopc block here..)

could anyone help me please?

best regards

Phate

resolved inserting streaming adapters and setting latency for streaming sink and source to 3.