dummy core between two VIP using SOPC builder

I suppose (but I'm not sure) that it's due to the readwrite latency transfer.

looking at the avalon spec, the ready latency shows when data wil be read(or write) to that sink.

when a block asserts din ready, the previous is set to assert datavalid andoter signals one clock cicle later (ready latency=1, so the next clock cicle)

Using registered ports adds at least two clock cycles latency (one cycle to read and one to write), so when te previous block in the data path will receive the din ready, next block won't be in a din ready state.

Hope i am not wrong and that I'd been clear enough!

best regards

phate.