Honored Contributor
Honored ContributorI made a similar decoder time ago in verilog, it seems to work.
Here it is, if you still need it. module vip_decoder ( input wire clock, // clock.clk input wire reset, // .reset // sinkA input din0_endofpacket, input din0_startofpacket, input din_ready, input din0_valid, input [15:0] din0_data, output enable ); reg go = 1'b0; reg [4:0] check_sop; reg din_ready_i, din0_endofpacket_i, din0_startofpacket_i, din0_valid_i; always@(posedge clock)begin if (go==0) begin if (din0_startofpacket) begin check_sop = din0_data[4:0]; if((check_sop==4'b0)&(din0_valid)) go=1'b1; end end//end if go == 0 else if (go==1'b1) begin if (din0_endofpacket) go = 1'b0; end end//end always@posedge clock assign enable = go; endmodule N.B. I know it coul be mde better , but for my sake, it worked!. Best regards Phate. p.s. this is a modified versione, the original one i made had both the sink and the source and all the others signals. Right now, I can't find the other bloks I wrote. I didn't work on FPGA for three or foru months, so I have to find them.
