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Altera_Forum's avatar
Altera_Forum
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15 years ago

dummy core between two VIP using SOPC builder

Hi all I am working on a simple Verilog block that should interface with avalon-ST and avalon-ST protocol. right now, the code I've written for sopc builder is this --- Quote Start --- ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, thanks. I was asking because I run into the exact same thing.. assigns go through no problem but registered wouldn't...

I'm trying to understand why these adapters would be required in a simple pass-through logic though. The timing relationships shouldn't change inside the block at all and all control packets should go through without issues too as long as the 4 lsbs are kept intact.. still learning.