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mfortuna's avatar
mfortuna
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4 days ago

DDR4 Problem Migrating from Arria 10 016 to 048

We have a board design that supports an F29 package Arria 10. It has two DDR4 interfaces running at an 1866 data rate.

In the past an 016 chip with DDR4-2400 ICs worked fine.

We needed more logic so we migrated to an 048. Because of parts availability we had to migrate to DDR-3200 ICs.

The board layout has not changed and we believe the various power supplies and clocks are working fine.

The 048 design fails calibration and won't even allow running "EMIF toolkit - Create Memory Interface." It hangs and times out. If I turn off address / command leveling the design still fails calibration but now I can create a memory interface and see the calibration results which show a complete failure with write and read margins. The design is badly broken but we don't know if it is the 048 or DDR4, or a combination of both. The DDR4 IP was regenerated and adjusted for the DDR4-3200 ICs.

We do see PLL lock with signaltap and can actually run Efficiency monitor. So the core is supplying a good clock to the fabric.

Any suggestions are welcome!

Thanks,

Mike

Memory

2 Replies

  • mfortuna's avatar
    mfortuna
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    1 hour ago

    I built the example design and it fails the same way. If I enable address/command leveling EMIF toolkit hangs. If I disable address/command leveling, the toolkit reports write-per-bit deskew failed. 

    The 016 based board works fine.

    Another datapoint is the 048 works fine except for DDR4. The design has PCIe Gen3 x 8 and four 12.5G transceivers. The boards were designed with the upgrade from 016 to 048 in mind.

    I did see another user had intermittent errors with an Arria 10 and DDR4-3200. But they were able to calibrate.

    Address command leveling is pretty basic. write-per-bit deskew may be a red herring.

     

  • yoichiK_altera's avatar
    yoichiK_altera
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    13 hours ago

    I can think of the cause is only power capability issue across migration devices.    Especially static power will increase from 016 -> 048 density.   Do you use the single DDR4 example design to see the calibration result ?