New Contributor
New ContributorI decided to try very basic testing of the 016 and 048 example designs.
The 016 design drives mem_cs_n to 1.2V and pulses it low at a regular rate, presumably refresh. If I rerun calibration using emif toolkit, I see lots of activity on on mem_cs_n.
The 048 design has mem_cs_n at 0.6V (due to termination). There is no activity. It appears the pin is not driven by the FPGA.
The 048 and 016 have correct pinouts and bank voltages. I used a non-DDR4 048 design to drive the mem_cs_n pin with a square wave and it works fine.
It appears the build is broken. I tried both Quartus 22.4 and 23.2 and both produce the same results.
Not being able to build and run the example design appears to be a tool issue.
New ContributorDespite our best efforts of doing a BOM scrub and checking the board, the HW designer and I did not see two important resistors missing, namely the RZQin resistors for each bank of DDR. With those in place the design is up and running.
I know this is difficult for a SW tool to detect but hanging address / command leveling or reporting a write skew failure definitely is not helpful for debugging an issue.
The smoking gun, for anyone that has the issue, is the mem_cs_n pin is not driven to 1.2v and instead parks at the termination voltage.
