Forum Discussion
ContributorDDR3_CLK_DQS_SIGNALS_PIN_ASSIGNMENT
6 Replies
sstrellSuper Contributor
It doesn't look like the I/O standard is your issue. It looks like your pin location assignments are the problem.
SERMASWATHIKAHi
Thanks, I Have resolved my clock signal issue.(it is related port direction in top file)
now I am getting error for dq signals.
I am using 7A bank for ddr3 io mapping
I have properly configured that. the following error is reporting for the design,
- sstrell
Looks like that pin cannot be used for DQ. Are you doing this in Pin Planner? Have you set the view for x8/x9 to highlight the pins supported for these functions?
- SERMASWATHIKA
Hi,
Yes, I am doing it in pin planner only with the highlights of DQ pins. i have assigned in dq pins only. I am sharing pin details sheet with this. can you please help me to resolve this?
do we need to connect rzq signal to ground?
FPGA DEVICE: 5CGXFC5C6F27C7
To Direction Location I/O Bank VREF Group Fitter Location I/O Standard cas_n Output PIN_A9 7A B7A_N0 PIN_A9 SSTL-15 Class I ck[1] Output PIN_H12 7A B7A_N0 PIN_H12 Differential 1.5-V SSTL Class I ck[0] Output PIN_G15 7A B7A_N0 PIN_G15 Differential 1.5-V SSTL Class I ck_n[1] Output PIN_G11 7A B7A_N0 PIN_G11 Differential 1.5-V SSTL Class I ck_n[0] Output PIN_G14 7A B7A_N0 PIN_G14 Differential 1.5-V SSTL Class I cke Output PIN_D21 7A B7A_N0 PIN_D21 SSTL-15 Class I cs_n Output PIN_A16 7A B7A_N0 PIN_A16 SSTL-15 Class I dm[3] Output PIN_B17 7A B7A_N0 PIN_B17 SSTL-15 Class I dm[2] Output PIN_A18 7A B7A_N0 PIN_A18 SSTL-15 Class I dm[1] Output PIN_C22 7A B7A_N0 PIN_C22 SSTL-15 Class I dm[0] Output PIN_C12 7A B7A_N0 PIN_C12 SSTL-15 Class I dq[31] Bidir PIN_D13 7A B7A_N0 PIN_D13 SSTL-15 Class I dq[30] Bidir PIN_D15 7A B7A_N0 PIN_D15 SSTL-15 Class I dq[29] Bidir PIN_A11 7A B7A_N0 PIN_A11 SSTL-15 Class I dq[28] Bidir PIN_C14 7A B7A_N0 PIN_C14 SSTL-15 Class I dq[27] Bidir PIN_D11 7A B7A_N0 PIN_D11 SSTL-15 Class I dq[26] Bidir PIN_C19 7A B7A_N0 PIN_C19 SSTL-15 Class I dq[25] Bidir PIN_C9 7A B7A_N0 PIN_C9 SSTL-15 Class I dq[24] Bidir PIN_C18 7A B7A_N0 PIN_C18 SSTL-15 Class I dq[23] Bidir PIN_C17 7A B7A_N0 PIN_C17 SSTL-15 Class I dq[22] Bidir PIN_D16 7A B7A_N0 PIN_D16 SSTL-15 Class I dq[21] Bidir PIN_E19 7A B7A_N0 PIN_E19 SSTL-15 Class I dq[20] Bidir PIN_C10 7A B7A_N0 PIN_C10 SSTL-15 Class I dq[19] Bidir PIN_M12 7A B7A_N0 PIN_M12 SSTL-15 Class I dq[18] Bidir PIN_N12 7A B7A_N0 PIN_N12 SSTL-15 Class I dq[17] Bidir PIN_C15 7A B7A_N0 PIN_C15 SSTL-15 Class I dq[16] Bidir PIN_C20 7A B7A_N0 PIN_C20 SSTL-15 Class I dq[15] Bidir PIN_B21 7A B7A_N0 PIN_B21 SSTL-15 Class I dq[14] Bidir PIN_A24 7A B7A_N0 PIN_A24 SSTL-15 Class I dq[13] Bidir PIN_B9 7A B7A_N0 PIN_B9 SSTL-15 Class I dq[12] Bidir PIN_E10 7A B7A_N0 PIN_E10 SSTL-15 Class I dq[11] Bidir PIN_B19 7A B7A_N0 PIN_B19 SSTL-15 Class I dq[10] Bidir PIN_F16 7A B7A_N0 PIN_F16 SSTL-15 Class I dq[9] Bidir PIN_E15 7A B7A_N0 PIN_E15 SSTL-15 Class I dq[8] Bidir PIN_A13 7A B7A_N0 PIN_A13 SSTL-15 Class I dq[7] Bidir PIN_A23 7A B7A_N0 PIN_A23 SSTL-15 Class I dq[6] Bidir PIN_G12 7A B7A_N0 PIN_G12 SSTL-15 Class I dq[5] Bidir PIN_B11 7A B7A_N0 PIN_B11 SSTL-15 Class I dq[4] Bidir PIN_B10 7A B7A_N0 PIN_B10 SSTL-15 Class I dq[3] Bidir PIN_A21 7A B7A_N0 PIN_A21 SSTL-15 Class I dq[2] Bidir PIN_A17 7A B7A_N0 PIN_A17 SSTL-15 Class I dq[1] Bidir PIN_A12 7A B7A_N0 PIN_A12 SSTL-15 Class I dq[0] Bidir PIN_A8 7A B7A_N0 PIN_A8 SSTL-15 Class I dqs[3] Bidir PIN_J12 7A B7A_N0 PIN_J12 Differential 1.5-V SSTL Class I dqs[2] Bidir PIN_L12 7A B7A_N0 PIN_L12 Differential 1.5-V SSTL Class I dqs[1] Bidir PIN_M11 7A B7A_N0 PIN_M11 Differential 1.5-V SSTL Class I dqs[0] Bidir PIN_H18 7A B7A_N0 PIN_H18 Differential 1.5-V SSTL Class I dqs_n[3] Bidir PIN_J11 7A B7A_N0 PIN_J11 Differential 1.5-V SSTL Class I dqs_n[2] Bidir PIN_K11 7A B7A_N0 PIN_K11 Differential 1.5-V SSTL Class I dqs_n[1] Bidir PIN_L11 7A B7A_N0 PIN_L11 Differential 1.5-V SSTL Class I dqs_n[0] Bidir PIN_H17 7A B7A_N0 PIN_H17 Differential 1.5-V SSTL Class I odt Output PIN_E11 7A B7A_N0 PIN_E11 SSTL-15 Class I ras_n Output PIN_B20 7A B7A_N0 PIN_B20 SSTL-15 Class I
AdzimZM_AlteraRegular Contributor
Hi,
Have you check out the pin placement for DDR3 in Pin-Out file?
If not, you may download it in this page: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#cyclone%C2%AEvdevices
For your selected device, the Pin-Out file should be 5CGXFC5.
Also can download with this link: https://cdrdv2.intel.com/v1/dl/getContent/657074
Regards,
Adzim
- AdzimZM_Altera
As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
