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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

DDR3_CLK_DQS_SIGNALS_PIN_ASSIGNMENT

Hi team,  I have tried to check the pin assignments with design files. I am getting error for DDR3 signals I/O Standard. Initially, I have configured the ddr3 I/Os with SSTL-15 CLASS I. when I ...
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sstrell's avatar
sstrell
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2 years ago

Looks like that pin cannot be used for DQ. Are you doing this in Pin Planner? Have you set the view for x8/x9 to highlight the pins supported for these functions?

SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

Hi,

Yes, I am doing it in pin planner only with the highlights of DQ pins. i have assigned in dq pins only. I am sharing pin details sheet with this. can you please help me to resolve this?

do we need to connect rzq signal to ground?

FPGA DEVICE: 5CGXFC5C6F27C7

ToDirectionLocationI/O BankVREF GroupFitter LocationI/O Standard
cas_nOutputPIN_A97AB7A_N0PIN_A9SSTL-15 Class I
ck[1]OutputPIN_H127AB7A_N0PIN_H12Differential 1.5-V SSTL Class I
ck[0]OutputPIN_G157AB7A_N0PIN_G15Differential 1.5-V SSTL Class I
ck_n[1]OutputPIN_G117AB7A_N0PIN_G11Differential 1.5-V SSTL Class I
ck_n[0]OutputPIN_G147AB7A_N0PIN_G14Differential 1.5-V SSTL Class I
ckeOutputPIN_D217AB7A_N0PIN_D21SSTL-15 Class I
cs_nOutputPIN_A167AB7A_N0PIN_A16SSTL-15 Class I
dm[3]OutputPIN_B177AB7A_N0PIN_B17SSTL-15 Class I
dm[2]OutputPIN_A187AB7A_N0PIN_A18SSTL-15 Class I
dm[1]OutputPIN_C227AB7A_N0PIN_C22SSTL-15 Class I
dm[0]OutputPIN_C127AB7A_N0PIN_C12SSTL-15 Class I
dq[31]BidirPIN_D137AB7A_N0PIN_D13SSTL-15 Class I
dq[30]BidirPIN_D157AB7A_N0PIN_D15SSTL-15 Class I
dq[29]BidirPIN_A117AB7A_N0PIN_A11SSTL-15 Class I
dq[28]BidirPIN_C147AB7A_N0PIN_C14SSTL-15 Class I
dq[27]BidirPIN_D117AB7A_N0PIN_D11SSTL-15 Class I
dq[26]BidirPIN_C197AB7A_N0PIN_C19SSTL-15 Class I
dq[25]BidirPIN_C97AB7A_N0PIN_C9SSTL-15 Class I
dq[24]BidirPIN_C187AB7A_N0PIN_C18SSTL-15 Class I
dq[23]BidirPIN_C177AB7A_N0PIN_C17SSTL-15 Class I
dq[22]BidirPIN_D167AB7A_N0PIN_D16SSTL-15 Class I
dq[21]BidirPIN_E197AB7A_N0PIN_E19SSTL-15 Class I
dq[20]BidirPIN_C107AB7A_N0PIN_C10SSTL-15 Class I
dq[19]BidirPIN_M127AB7A_N0PIN_M12SSTL-15 Class I
dq[18]BidirPIN_N127AB7A_N0PIN_N12SSTL-15 Class I
dq[17]BidirPIN_C157AB7A_N0PIN_C15SSTL-15 Class I
dq[16]BidirPIN_C207AB7A_N0PIN_C20SSTL-15 Class I
dq[15]BidirPIN_B217AB7A_N0PIN_B21SSTL-15 Class I
dq[14]BidirPIN_A247AB7A_N0PIN_A24SSTL-15 Class I
dq[13]BidirPIN_B97AB7A_N0PIN_B9SSTL-15 Class I
dq[12]BidirPIN_E107AB7A_N0PIN_E10SSTL-15 Class I
dq[11]BidirPIN_B197AB7A_N0PIN_B19SSTL-15 Class I
dq[10]BidirPIN_F167AB7A_N0PIN_F16SSTL-15 Class I
dq[9]BidirPIN_E157AB7A_N0PIN_E15SSTL-15 Class I
dq[8]BidirPIN_A137AB7A_N0PIN_A13SSTL-15 Class I
dq[7]BidirPIN_A237AB7A_N0PIN_A23SSTL-15 Class I
dq[6]BidirPIN_G127AB7A_N0PIN_G12SSTL-15 Class I
dq[5]BidirPIN_B117AB7A_N0PIN_B11SSTL-15 Class I
dq[4]BidirPIN_B107AB7A_N0PIN_B10SSTL-15 Class I
dq[3]BidirPIN_A217AB7A_N0PIN_A21SSTL-15 Class I
dq[2]BidirPIN_A177AB7A_N0PIN_A17SSTL-15 Class I
dq[1]BidirPIN_A127AB7A_N0PIN_A12SSTL-15 Class I
dq[0]BidirPIN_A87AB7A_N0PIN_A8SSTL-15 Class I
dqs[3]BidirPIN_J127AB7A_N0PIN_J12Differential 1.5-V SSTL Class I
dqs[2]BidirPIN_L127AB7A_N0PIN_L12Differential 1.5-V SSTL Class I
dqs[1]BidirPIN_M117AB7A_N0PIN_M11Differential 1.5-V SSTL Class I
dqs[0]BidirPIN_H187AB7A_N0PIN_H18Differential 1.5-V SSTL Class I
dqs_n[3]BidirPIN_J117AB7A_N0PIN_J11Differential 1.5-V SSTL Class I
dqs_n[2]BidirPIN_K117AB7A_N0PIN_K11Differential 1.5-V SSTL Class I
dqs_n[1]BidirPIN_L117AB7A_N0PIN_L11Differential 1.5-V SSTL Class I
dqs_n[0]BidirPIN_H177AB7A_N0PIN_H17Differential 1.5-V SSTL Class I
odtOutputPIN_E117AB7A_N0PIN_E11SSTL-15 Class I
ras_nOutputPIN_B207AB7A_N0PIN_B20SSTL-15 Class I