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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

DDR3_CLK_DQS_SIGNALS_PIN_ASSIGNMENT

Hi team,  I have tried to check the pin assignments with design files. I am getting error for DDR3 signals I/O Standard. Initially, I have configured the ddr3 I/Os with SSTL-15 CLASS I. when I ...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

It doesn't look like the I/O standard is your issue. It looks like your pin location assignments are the problem.

  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    Hi

    Thanks, I Have resolved my clock signal issue.(it is related port direction in top file)

    now I am getting error for dq signals.

    I am using 7A bank for ddr3 io mapping

    I have properly configured that. the following error is reporting for the design,