Forum Discussion
Honored ContributorCVO frequency
I have a design that uses a CVO. This is in a Stratix III part. The User Guide states that the CVO should be able to run around 271 - 317MHz depending on it's configuration. I'm able to approach this frequency as far as running the chain of IP but when I clock the video out of the CVO Time Quest is telling me a maximum frequency of around 170 - 180MHz. Does anyone have any thoughts on this? I need to run my output clock around 260MHz which I thought I could hit per the User Guide but the tools are telling me differently. Thanks.
14 Replies
Altera_Forumdid you add the .sdc constraints file for the CVO from $QUARTUS_ROOTDIR/../ip/altera/clocked_video_output? there are some false paths that may help timing
can you paste the first couple failing paths?- Altera_Forum
You may also want to double check what the maximum output frequency for the I/O standard you are using is in the device data sheet. Some I/O standards may support a much lower frequency than the internal FPGA logic. There may be relevant I/O assignment settings you can change to increase the output frequency.
- Altera_Forum
Hey guys. Thanks for your input. I'll check the constraints this morning. My FAE was in yesterday and he alluded to what Kevin said. This IP was set up for a maximum of 1080p so probably about 148.5MHz. From looking at the Time Quest output he suggested making our own CVO that maybe we could run faster. He thought there was a big adder in the path that could be coded better. So that's the path going forward.
I've included a .bmp of the Time Quest output. - Altera_Forum
Also - so I need to add a path for the .sdc for every IP that I use? I guess I assumed this would be automatic.
- Altera_Forum
I added in the .sdc for the CVO and my worst case slack went from -1.468 to -0.259. So that's quite an improvement. Still not where I need to be but much closer. Sorry the .bmp doesn't show up very well.
From Node: tx:InstTx|VipCvo:the_VipCvo|VipCvo_GN:auto_inst|alt_vip_IS2Vid:vipcvo|alt_vip_common_generic_count:v_counter|count[10] To Node: tx:InstTx|VipCvo:the_VipCvo|VipCvo_GN:auto_inst|alt_vip_IS2Vid:vipcvo|reset_counters Is the worst case path. - Altera_Forum
yeah the bmp came up unreadable, was it resized by the forum?
there doesn't seem to be a rule on when you need .sdc files. some get generated in the project directory, some are in the IP install directory, and some are embedded in the core which speed grade SIII and QII version are you using? i'm doing a 1080p design in SIV and i haven't had timing issues. i recommend filing a service request before or in parallel to creating your own CVO - Altera_Forum
No I resized it. It wouldn't let me upload anything bigger.
I did look for other .sdc files and the only ones I found missing were the CVI and CVO. We're in a SIII -3. We have hardware in the field so can't change the FPGA. Currently we're running 1080p without any problems but now we need to run higher resolutions. So far it has not been easy. Also I have not changed over to QII 10.0 yet. I loaded it on another machine and I did get a little improvement in timing there too. Thanks again for your input . - Altera_Forum
i misunderstood i thought you were targeting 1080p. i know someone going over 1080p as well, i'll ask how they approached the problem. you may need to build a CVO in this case
and i think CVI and CVO are the only VIP blocks with .sdc files, the rest should be in the SOPC .sdc - Altera_Forum
and i recommend the open source tool GIMP to edit, resize, and compress images :)
- Altera_Forum
...and for "mostly" text images, PNG generally works fine. That image is definitely unreadable. :-)
