Configuring triple speed ethernet MAC with National DP83848 PHY in MII interface

Hey guy,

First of all the attached JPG is too small and it is quite blur.

Second, have you ever successfully run a web server example design before (can be TSE or LAN9C111)? If you haven't, Then I guess, the "hang" that you say is not true. Whenever you start up the Web Server design, the alt_iniche_init() will be called, provided with the MAC address you enter, it will start doing DHCP to obtain a valid dynamic IP address, it will take a very long time before it timeout if your network don't have a DHCP server.

If that is the case and you don't have a network with DHCP server, I can provide you a work around to run Web Server with static IP, this is necessary for a PC to board point to point network connetion. If it is not, please provide a snapshot of the console text where the application hang,

Third, you don't need to do any custom settings on the PHY(including detection network speed and duplex mode), the TSE driver already do it for you during initialization time, it natively support this National PHY. One thing that you need to take note is, whenever you want to run TSE including small mac version, you need to turn on the byte shifting/byte alignment synthesis option in the hardware, else it won't work.

Lastly, look at the web server readme file, you can send or receive packet from the application using web browser. Else, you can also run simple socket server application, it allows you to do telnet access to the application. If you need access to the packet level information, installed a WireShark program on your laptop to peek on the packet.

Hi teilersen,

I have made my own custom Cyclone III Nios board with the DP83848 PHY and it works fine. I also used the TSE MAC from Altera.

I began with the simple socket server project and then I moved on the webserver project.

Did you success in your project?

I can help you if you have any questions..

Just a last thing, did you configure a system clock in SOPC builder, UCOSII and Interniche need this feature to work..

Regards,

-Pierre

Hi Pierre!

I sent you a private message with my dummy questions.

I would really appreciate your reply!

Thanks,

Tamas

Hi Tamas,

You got it! Your steps are right but you need to check that your PHY device is supported by the TSE (this is the most important!), if not try to find a MAC ip which support your PHY (if the board is already done).

Here is a summarize of the different ethernet "stuff" used in this project:

software:

operating system: UCOS/II (provided by altera for eval, you will need to purchase a license in your final product)

ip stack: Interniche (provided by altera for eval, you will need to purchase a license in your final product)

user code: "Simple Socket Server" template wich use ucos/II and Interniche

midware:

MAC IP TSE from Altera (free for eval) which is a vhdl entity to instantiate into your project, this ip will 'discuss" through MII bus with your PHY device

hardware:

Ethernet PHY (National DP83848C or Mrvell..) connected to your MAC ip hosted in the FPGA.

I'm not sure step 9 will work because I think ethernet templates from Altera and the TSE don't work in ISS mode. For my project I used directly my custom board (>run hardware).

If you success with the "simple socket server" template you can use easily the "webserver" template if your board has the appropriate memory configuration (flash to handle HTML pages)

I hope it will help you,

Don't hesitate if you any other questions (when you will have your board)

Regards,

-Pierre

Hi all,

Quick question about the PHY connection: is it necessary to take the TX & RX clock pins to global clocks netword on the Clkin pins on the FPGA (or DPCLKs), or can normal IO's be used?

Thanks,

Pierre Watts

Hi Pierre,

You can use I/Os. It works fine for me.

Best regards,

-Pierre

Thanks for the quick reply! One last question: the DP83848 isn't 100% clear on its 25MHz clock output. Since it has a power-on reset, that clock should be present upon powerup. Can this therefore be used to clock the FPGA and its PLL's directly, thereby eliminating the need for an extra oscillator for the FPGA? Or is this a little dangerous?

Thanks,

Pierre

Hello,

I'm back on FPGA stuff, a little bit late for the answer but anyway maybe it will be useful for other people on this forum. The FPGA should have its own oscillator (i.e 50mhz), the 25Mhz clock output seems to be a little bit dangerous... because this chip communicates with the FPGA and so... (chicken and egg story..). I have one oscillator for the FPGA and for the DP83848. If anyone try this configuration (providing clock from DP83848 to FPGA) please don't hesistate to leave a message.

Regards,

-Pierre

--- Quote Start ---

Hi teilersen,

I have made my own custom Cyclone III Nios board with the DP83848 PHY and it works fine. I also used the TSE MAC from Altera.

I began with the simple socket server project and then I moved on the webserver project.

Did you success in your project?

I can help you if you have any questions..

Just a last thing, did you configure a system clock in SOPC builder, UCOSII and Interniche need this feature to work..

Regards,

-Pierre

--- Quote End ---

Hi Pierre

my problem is as following:

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

=============== Software License Reminder ================

This software project uses an unlicensed version of the NicheStack TCP/IP

Network Stack - Nios II Edition. If you want to ship resulting object

code in your product, you must purchase a license for this software from

Altera. For information go to: "http://www.altera.com/nichestack"

=====================================================

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x00000400

INFO : PHY National DP83848C found at PHY address 0x1f of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 100, Duplex = Half

OK, x=0, CMD_CONFIG=0x01000000

MAC post-initialization: CMD_CONFIG=0x05000603

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

IP address of et1 : 0.0.0.0

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up

at the same time ， i don't know why the DP83848 is very hot?

thanks!