Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Configuring triple speed ethernet MAC with National DP83848 PHY in MII interface

Hi I am trying to make a design with a triple speed ethernet MAC from Altera work. I am using a National DP83848 PHY and the small 10/100 version of the MAC. I have attached a snapshot of my sc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for the quick reply! One last question: the DP83848 isn't 100% clear on its 25MHz clock output. Since it has a power-on reset, that clock should be present upon powerup. Can this therefore be used to clock the FPGA and its PLL's directly, thereby eliminating the need for an extra oscillator for the FPGA? Or is this a little dangerous?

Thanks,

Pierre