Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi Tamas,
You got it! Your steps are right but you need to check that your PHY device is supported by the TSE (this is the most important!), if not try to find a MAC ip which support your PHY (if the board is already done). Here is a summarize of the different ethernet "stuff" used in this project: software: operating system: UCOS/II (provided by altera for eval, you will need to purchase a license in your final product) ip stack: Interniche (provided by altera for eval, you will need to purchase a license in your final product) user code: "Simple Socket Server" template wich use ucos/II and Interniche midware: MAC IP TSE from Altera (free for eval) which is a vhdl entity to instantiate into your project, this ip will 'discuss" through MII bus with your PHY device hardware: Ethernet PHY (National DP83848C or Mrvell..) connected to your MAC ip hosted in the FPGA. I'm not sure step 9 will work because I think ethernet templates from Altera and the TSE don't work in ISS mode. For my project I used directly my custom board (>run hardware). If you success with the "simple socket server" template you can use easily the "webserver" template if your board has the appropriate memory configuration (flash to handle HTML pages) I hope it will help you, Don't hesitate if you any other questions (when you will have your board) Regards, -Pierre