Clock-Error --> Two ports have different clocks, where they should have the same

I have the same problem. Now i have replaced the Clock_derived block with a PLL but I can't configure it correctly.

The main clock is the 48kHz

The output clock has:

period multiplier = 32

period divider = 1

that should create a 1'536 MHz clock.

Error message into the PLL configuration window: Cannot implement configuration. Why? What is wrong? Is there somewhere an example?

Thanks in advance

I got the same problem in PLL configuration window:

---

Cannot implement configuration. Update multiplier and divider values and click "apply".

---

This message appears with all possible parameters. Any idea why? I am using Matlab 2010a and DSP-Builder v9.1.

I would like to generate a clock and feed it to various other blocks as input block. In the meantime I implemented a Quartus PLL clock with HDL-Import block. But with that solution I cant select this generated clock as input clocks for other blocks.

The background: My project needs to have one clock for all components. I also need to output this clock. But without being able to set parameters in the PLL configuration windows I can't achieve this.

MATLAB 2010a is only supported by DSP Builder 10.1+. i'm not sure if that is causing the issue you are seeing here but i have run into problems using 2010a when it wasn't yet supported

what device are you targeting? i also remember an issue with Cyclone IV GX PLLs in DSP Builder which should also be fixed in later software

Matlab 2010a and DSP-Builder v9.1 was the only possible combination for me. With any other combination I had trouble with SignalTap:

http://www.alteraforum.com/forum/showthread.php?p=111518

I am working with a Cyclone II DSP Development Board with a EP2C70. In my project I generade signals at specific frequencies and send them via 1xDAC to a resonator circuit. After the circuit I measure the signal on 1xADC.

Without any PLL my AD-converted signal is cluttered with peaks. The signal is fine if I use a PLL generated in Quartus and import it via the simulink block "HDL Import". The Altera Simulink Blockset PLL is useless for me, as it always outputs the error i posted above: "Cannot implement configuration. Update multiplier and divider values and click "apply"."

There still might be a problem with the quartus PLL as well. When I look at the signals right after the DAC with a spectrum analyser I see that the signal actually are shifted in frequency. When I try to get a 11.992000 MHz output i actually get about 11.998 MHz. This frequency shift depends on the actual frequency I'm aiming at. Only a shift < 200 Hz is tolerable for my project. But actually I got several KHz.

It is not a mather of uncontinuity any more:

http://www.alteraforum.com/forum/showthread.php?t=28510

So, my guess: the problem is caused by using two different clocks for the different parts. The ADCs and DACs are clocked by the quartus-vhdl-pll and anything else (LUT, Counter, ...) is clocked directly via oscillator. Why? because I cant set the generated clocks by the quartus-vhdl-pll as an input to LUT, Counter, ...

And last but not least, that's the reason why I would like to be able to use the Simulink Altera Blockset PLL.

I hope my situation is more understandable, now.

The issue is almost certainly nothing to do with the MATLAB version. You say you tried all possible configurations but does that include varying the base clock frequency?

An example working PLL design can be found in quartus\dsp_builder\DesignExamples\Tutorials\MultiRate\Pll\MultipleClockDelay.mdl. The main way I can get that design to fail in the way you describe is to change the base clock to something very slow (like 48KHz which is probably the problem Bonil had above).

Thanks for the hint.

I just tried to use this example with my board. And it does not work.

When I use the Tutorial everything is fine. But when I switch the boad and device type to Cyclone II inside the Signal Compiler, save the Model and then try to update the PLL I get the error in my first post. When I switch back to the default device "Stratix II" the error is gone. But I only can use a Cyclone II. So i can't use the PLL Block. :(

Does this problem occour at anybody else? Does it also not happen with Stratix II?

Yes, I also tried different base clocks in between 50 and 125 MHz.

Perhaps, you should check the data sheet for the Cyclone II device and verify what frequencies it supports.

By trial and error, I've found that the PLL block reports that it's unable to implement the configuration if the Ouput period exceeds 100ns. There are other circumstances where it fails, but the data sheet should say what's allowed.