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Altera_Forum
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16 years ago

Clock-Error --> Two ports have different clocks, where they should have the same

Hi People, I make a filterbank with 32 IIR-bandpassfilter --> 32x16 coefficient. the application is a mp3-encoder/decoder in dsp-builder. I have resolt my schematic with LUT for reduce mul...
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Altera_Forum
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15 years ago

Thanks for the hint.

I just tried to use this example with my board. And it does not work.

When I use the Tutorial everything is fine. But when I switch the boad and device type to Cyclone II inside the Signal Compiler, save the Model and then try to update the PLL I get the error in my first post. When I switch back to the default device "Stratix II" the error is gone. But I only can use a Cyclone II. So i can't use the PLL Block. :(

Does this problem occour at anybody else? Does it also not happen with Stratix II?

Yes, I also tried different base clocks in between 50 and 125 MHz.