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Altera_Forum
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16 years ago

Clock-Error --> Two ports have different clocks, where they should have the same

Hi People, I make a filterbank with 32 IIR-bandpassfilter --> 32x16 coefficient. the application is a mp3-encoder/decoder in dsp-builder. I have resolt my schematic with LUT for reduce mul...
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Altera_Forum
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14 years ago

I want to use it at it's highest possible clock rate as written in the DSP Developemnt Kit Manual. 125 MHz. It's just not possible via the Altera Simulink PLL. If I implement a PLL in Quartus II for this device, there is no problem at all.