Clock-Error --> Two ports have different clocks, where they should have the same

The issue is almost certainly nothing to do with the MATLAB version. You say you tried all possible configurations but does that include varying the base clock frequency?

An example working PLL design can be found in quartus\dsp_builder\DesignExamples\Tutorials\MultiRate\Pll\MultipleClockDelay.mdl. The main way I can get that design to fail in the way you describe is to change the base clock to something very slow (like 48KHz which is probably the problem Bonil had above).