Honored Contributor
Honored ContributorMatlab 2010a and DSP-Builder v9.1 was the only possible combination for me. With any other combination I had trouble with SignalTap:
http://www.alteraforum.com/forum/showthread.php?p=111518 I am working with a Cyclone II DSP Development Board with a EP2C70. In my project I generade signals at specific frequencies and send them via 1xDAC to a resonator circuit. After the circuit I measure the signal on 1xADC. Without any PLL my AD-converted signal is cluttered with peaks. The signal is fine if I use a PLL generated in Quartus and import it via the simulink block "HDL Import". The Altera Simulink Blockset PLL is useless for me, as it always outputs the error i posted above: "Cannot implement configuration. Update multiplier and divider values and click "apply"." There still might be a problem with the quartus PLL as well. When I look at the signals right after the DAC with a spectrum analyser I see that the signal actually are shifted in frequency. When I try to get a 11.992000 MHz output i actually get about 11.998 MHz. This frequency shift depends on the actual frequency I'm aiming at. Only a shift < 200 Hz is tolerable for my project. But actually I got several KHz. It is not a mather of uncontinuity any more: http://www.alteraforum.com/forum/showthread.php?t=28510 So, my guess: the problem is caused by using two different clocks for the different parts. The ADCs and DACs are clocked by the quartus-vhdl-pll and anything else (LUT, Counter, ...) is clocked directly via oscillator. Why? because I cant set the generated clocks by the quartus-vhdl-pll as an input to LUT, Counter, ... And last but not least, that's the reason why I would like to be able to use the Simulink Altera Blockset PLL. I hope my situation is more understandable, now.
