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Altera_Forum
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16 years ago

Clock-Error --> Two ports have different clocks, where they should have the same

Hi People, I make a filterbank with 32 IIR-bandpassfilter --> 32x16 coefficient. the application is a mp3-encoder/decoder in dsp-builder. I have resolt my schematic with LUT for reduce mul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I have the same problem. Now i have replaced the Clock_derived block with a PLL but I can't configure it correctly.

The main clock is the 48kHz

The output clock has:

period multiplier = 32

period divider = 1

that should create a 1'536 MHz clock.

Error message into the PLL configuration window: Cannot implement configuration. Why? What is wrong? Is there somewhere an example?

Thanks in advance