ContributorHi
My version of Quartus Prime is 22.3
I try to generate clock control IP for the device startix 10
When I define 2 input clocks the option to ensure glitch free changed to gray and I get message that this feature isn't supported by this Quartus release as you see below :
My question is : When will you intend to enable this option ? I need it for my design
Regular ContributorHi,
Thank you for reaching out Intel FPGA Community.
If you refer to the Clock Control Block (ALTCLKCTRL) IP Core User Guide, it has mention that when you are using the glitch free switchover feature, the clock you are switching from must be active. If it is not active, the switchover circuit will not be able to transition from the clock you originally selected. Refer link below for the user guide:
Regards,
Aqid
ContributorHi
Your answer relevant to opertinal work with the this :
when you are using the glitch free switchover feature, the clock you are switching from must be active. If it is not active, the switchover circuit will not be able to transition from the clock you originally selected. Refer link below for the user guide
But my question is about the ability to enable the option of " ensure glitch free clock switchover "
I dont have the option enable this option at all and I get message that this feature isn't supported by this Quartus (my ver is 22.3)
When will you intend to enable this option ? which version this option will suuport ?
Yishay
Super ContributorNot sure why you're going through this again. The feature is not available in S10 as discussed in your prior post: https://community.intel.com/t5/FPGA-Intellectual-Property/Glitch-less-clock/m-p/1437771.
Contributorsure ,
Just want to know when will you intend to enable this option at this device
Super ContributorAs stated by Intel at the bottom of your last post, the feature is simply not available in Stratix 10 so it will never get enabled there.
ContributorThank you
You can close this case
Occasional ContributorHi
at the bottom of the post "https://community.intel.com/t5/FPGA-Intellectual-Property/Glitch-less-clock/m-p/1437771"
is written " glitch free clock switchover option is not available in any of the Clock Control IP for Stratix 10 at the moment "
therefore it was not clear if there is any Stx10 - HW constraint that prevents from implementing it ... or it will be implemented in the future ...
moreover the error you are getting from Quartus (once trying to enable the glitch free" ) is error related to "Quartus Version" and not to the Stx10 HW which is used - which increase the confusion .
anyway - the answer is clear now - that in Stx10 there is no glitch free mux now and in the future .
Or.
