Forum Discussion
ymiler
Contributor
Contributorclock control intel FPGA IP
Hi
My version of Quartus Prime is 22.3
I try to generate clock control IP for the device startix 10
When I define 2 input clocks the option to ensure glitch free changed to gray and I get...
sstrell
Super Contributor
Super ContributorNot sure why you're going through this again. The feature is not available in S10 as discussed in your prior post: https://community.intel.com/t5/FPGA-Intellectual-Property/Glitch-less-clock/m-p/1437771.
- ymiler
sure ,
Just want to know when will you intend to enable this option at this device
