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ymiler's avatar
ymiler
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3 years ago

clock control intel FPGA IP

Hi My version of Quartus Prime is 22.3 I try to generate clock control IP for the device startix 10 When I define 2 input clocks the option to ensure glitch free changed to gray and I get...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

As stated by Intel at the bottom of your last post, the feature is simply not available in Stratix 10 so it will never get enabled there.

  • ymiler's avatar
    ymiler
    Icon for Contributor rankContributor
    3 years ago

    Thank you

    You can close this case

  • OrF's avatar
    OrF
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi

    at the bottom of the post "https://community.intel.com/t5/FPGA-Intellectual-Property/Glitch-less-clock/m-p/1437771"

    is written " glitch free clock switchover option is not available in any of the Clock Control IP for Stratix 10 at the moment "

    therefore it was not clear if there is any Stx10 - HW constraint that prevents from implementing it ... or it will be implemented in the future ...

    moreover the error you are getting from Quartus (once trying to enable the glitch free" ) is error related to "Quartus Version" and not to the Stx10 HW which is used - which increase the confusion .

    anyway - the answer is clear now - that in Stx10 there is no glitch free mux now and in the future .

    Or.