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Honored Contributor
Honored ContributorAvalon ST custom IP component
Hello,
I'm having trouble creating my own component that uses Avalon Streaming Interface in QSys. Based on the VIP demonstartion for DE1-SoC I want to have a connection between the Altera VIP Frame Reader and Alpha Blending Mixer (to process the frames that are sent). In order to do that I created a VHDL file and created a new component in QSys, specyfing the data, valid, ready, startofpacket and endofpacket signals since these are the ones used by Frame Reader and Blending Mixer. I check if the valid and ready signals are asserted and then just pass the data, startofpacket and endofpacket signals through. In QSys I also needed to add Timing Adapters before and after my component because of Ready Latency. Unfortunately, the frames flows continously and are moving through the vga screen so I believe there's something wrong with the logic in my component. I check the signals at the rising edge of the clock. I'm new to the Avalon stuff and I'm sure I'm missing something really simple in the code. I attach it below. Could you help me find what's missing in here?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY simple_avalon_interface IS
PORT (
clock, resetn : IN STD_LOGIC;
din_startofpacket : in std_logic;
din_endofpacket : in std_logic;
din_valid : in std_LOGIC;
din_ready : out STD_LOGIC;
din_data : in STD_LOGIC_VECTOR(23 DOWNTO 0);
dout_startofpacket : out std_logic;
dout_endofpacket : out std_logic;
dout_valid : out std_LOGIC;
dout_ready : in STD_LOGIC;
dout_data : out STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END simple_avalon_interface;
ARCHITECTURE Structure OF simple_avalon_interface IS
BEGIN
process (clock,dout_ready,din_valid)
begin
if (rising_edge(clock)) then
if (dout_ready ='1' and din_valid = '1') then
dout_valid <= '1';
din_ready <= '1';
dout_data <= din_data;
dout_startofpacket <= din_startofpacket;
dout_endofpacket <= din_endofpacket;
else
dout_valid <= '0';
din_ready <= '0';
end if;
end if;
end process;
END Structure;
